FIG. 1 is an illustration of a color CMOS active pixel sensor (APS) system 100. The system 100 includes a N×M pixel array 101 comprised of pixels R, G, B respectively sensitive to red, green, and blue colored light. The pixels R, G, B are arranged in a Bayer pattern which models human visual response. In the Bayer pattern, alternating rows are comprised of green/red and green/blue pixels. Any image focused upon the pixel array causes the individual pixels to convert the incident light into electrical charge. Conventionally, each pixel outputs two signals, including a reset signal corresponding to a baseline voltage level, as well a photo signal corresponding to the base line voltage as modified by charge accumulation in the pixel (caused by incident light). These two signals may be considered as different components of a single differential signal, i.e., a pixel signal. The APS system 100 operates by reading the pixel signals of each row, one at a time, from the N×M pixel array to a N×1 row of pixel buffers 102. The pixels in each row are connected to respective column pixel buffers 102 designed to sample and hold both the reset and photo column signals output by the pixels of the array 101, and may be implemented, for example, using a plurality of sample-and-hold circuits. More specifically, the reset signal (Vrst) of each pixel in the current row is read into the row of pixel buffers 102, and then the photo signal (Vsig) of each pixel is then read into the row of pixel buffers 102.
The N×1 row of pixel buffers 102 are output to a N:1 multiplexer 103, which is used to sequentially select a column pixel output from the N×1 row of pixels for further processing by the analog signal processing chain 104. The analog signal processing chain 104 includes a variable gain stage which amplifies the differential pixel signals which arc sequentially presented to multiplexer 103 to the extent required so that the amplified pixel signal will match well with the input to the analog-to-digital converter 106. The amplified signals arc then supplied to the analog-to-digital converter 106, which converts the amplified voltages to a digital value, which is stored in buffer 107.
The above described process is repeated for each pixel in the N×1 row. When the last pixel has been processed, the procedure is repeated using another row, until each row of the pixel array has been processed. Once the digital values have been stored in the buffer, the digital processor 108 further processes values stored in the buffer. Such processing may include, for example, color interpolation, resolution scaling, noise reduction, white balance adjustment, or any other commonly performed pixel processing. The processed digital image can then be stored in a storage device 109. A controller 110 is used to coordinate the timing of the operations discussed.
An issue associated with a pixel read out system of the type illustrated in FIG. 1 is the power consumption of the analog signal chain 104. FIG. 2 is an illustration of a typical amplification stage 200 which may be found in an analog signal chain 104. The amplification stage 200 includes two substages 210, 220 coupled in series. Each stage is configured as a differential amplifier because the pixel signal is assumed to be a differential signal with Vrst on one input and Vsig on another. However, some imaging systems use single ended signals (where the Vrst and Vsig signals are subtracted before amplification) and would therefore use substages having single ended amplifiers.
The first substage 210 includes input terminals 211 which arc coupled to input capacitors 212 via switch 211a. The input capacitors are selectively coupled via switches 213 to the inputs of an amplifier 214. The outputs of the amplifier 214 are coupled as inputs to the second substage 220. Additionally, the outputs of the amplifier 214 arc also provided to a pair of feedback loops. The feedback loops include feedback capacitors 215, 216, each of which may be selectively coupled to the feedback loops via the states of switches 217, 218. Finally, reset switches 219 are used to selectively reset the amplifier by shorting across the feedback loop. The gain of the first substage 210 is proportional to the input capacitance divided by total feedback capacitance. In many instances, capacitors 215 and 216 have the same capacitance. Thus, the switches 217, 218 may be used to set the feedback loop capacitance to two non-zero values. The first substage 210, as illustrated, therefore provides for two levels of amplifier gain, depending upon the state of switches 217, 218. In many implementations, the first substage 210 is designed to provide a selectable gain of approximately 1.0 or approximately 2.0.
The second substage 220 include input capacitors 222 which arc coupled to the inputs of amplifier 224. The outputs of the amplifier 224 is provided as the output of the amplification stage 200. Additionally, the outputs of the amplifier 224 are also provided to form a pair of feedback loops. The feedback loops include capacitors 225. Reset switches 229 are provided to reset the second substage 220 by shorting across the feedback loops. Typically, reset switches 219 and 229 arc controlled by the same control signal, so that both substages 210, 220 are reset at the same time. One difference between the first 210 and second 220 substages is that input capacitors 222 and feedback capacitors 225 in the second substage 220 are variable capacitors. The use of variable capacitors permits the capacitance of the input and feedback capacitors to be controlled with a finer granularity. For example, in many implementations, the second substage 220 is designed to provide a selectable gain ranging from approximately 1.0 to approximately 8.0 in finer (e.g., 1/16th gain) increments. The controller 110 (FIG. 1) may be used to control the selected gain level in both stages 210, 220.
Gain-bandwidth refers to an amplifier parameter which is proportional to both gain and bandwidth. In an amplifier, bandwidth is related to settling time, or the time required for the amplifier to produce a stable output signal from an input signal. Amplifiers 214, 224 must support a bandwidth which corresponds to a settling time which is at least equal to the timing requirements of the inputs to analog-to-digital converter 106. In similar amplifiers, such as a multiple gain amplifier operated at any one of its supported gain levels, the gain-bandwidth remains constant. Amplifiers 214, 224 therefore operate at the minimum required bandwidth at the highest gain level, and operate a higher bandwidths at lower gain levels.
That is, amplification substages which are designed to accommodate a wide range of gains are required to operate at a high level of gain-bandwidth and have a correspondingly high level of power consumption. Indeed, in a multi-gain amplification substage excess power is being consumed whenever the substage is not being operated at peak gain because an amplifier capable of being operated at maximum gain while meeting the minimum bandwidth requirement will operate at a bandwidth exceeding the minimum bandwidth requirement whenever the gain of the amplifier is below the maximum supported gain, since the gain bandwidth of the amplifier remains constant. If it is assumed that each gain level has an equal chance of being the appropriate gain level to match the pixel signal for color correction and/or analog to digital conversion, it can be seen that amplifiers which operate at a wide range of discrete gain levels spend most of their time at a gain level where excess power is consumed. In some CMOS APS sensor systems, approximately one third of the total sensor power consumption can be attributed to the power dissipated in the analog signal chain 104 and specifically in the FIG. 2 amplifier stage 200. Accordingly, there is a need and desire for a more efficient method and apparatus for amplifying a pixel signal.